This is my first time hearing that you can stack logic transistors on top of each other, so I'm kind of interested to see how this technology pans out (or if it /does/ pan out). Usually, chips are designed using laser lithography, which essentially burns away part of a chip and prints silicon in the newly-blasted trenches. At least this is how they've been making them for decades.
Obviously the major drawback to this is that you can't really "stack" transistors on top of each other without physically stacking the wafers. Put simply, a laser can only blast away the surface of a wafer, so how could it create multiple layers? I think that's the part I'm missing, so I'll need to read more on how they mass-manufacture something like this!
I think put even more simply, this breakthrough is enticing because if you stack transistors, it's like taking an elevator to another floor instead of walking to a different office across the street (and since electricity is literally limited by the speed of light, then theoretically reducing the distance between transistors could increase the clock speed).
As you said, in practice the technology is going to need more time to mature, so I'm interested in reading more about this as more is developed.
Your elevator analogy is basically the whole pitch. Shorten the path a signal has to travel and you stop paying the speed-of-light tax on it, so the chip can run faster at the same power. That's the entire reason anyone's chasing this.
The piece you might be missing is smaller than it feels. Chips get built from the bottom up, more like a 3D printer, printing in reverse, rather than a sculptor; each ultra-thin layer is laid down on top of the last one. The light's only job is to pattern a stencil that decides where the next material goes, and the silicon itself stays untouched. The extra layers just come from stacking upward over and over, which the industry's quietly been doing for decades.
The catch, and why this might not pan out, is a thermal trap. The wiring already stacks 20-ish layers like this no problem. Stacking the actual transistors is the hard part, because making a good transistor means baking the silicon screaming hot, and baking a second layer that hot cooks the finished one sitting underneath it. Bake cooler to spare the bottom and the top layer comes out slow. Add the yield problem, where you bond two wafers and a single defect on either one ruins both, and you've got a real wall.
So I definitely agree it at least needs time. And that’s what the reference flow is for; plug in real public chip numbers and check whether the speed you'd actually gain beats the heat and yield penalties, instead of taking a lab-demo headline at face value. I'd love to see someone crack it, but so far the flat chip keeps winning that math.
This is my first time hearing that you can stack logic transistors on top of each other, so I'm kind of interested to see how this technology pans out (or if it /does/ pan out). Usually, chips are designed using laser lithography, which essentially burns away part of a chip and prints silicon in the newly-blasted trenches. At least this is how they've been making them for decades.
Obviously the major drawback to this is that you can't really "stack" transistors on top of each other without physically stacking the wafers. Put simply, a laser can only blast away the surface of a wafer, so how could it create multiple layers? I think that's the part I'm missing, so I'll need to read more on how they mass-manufacture something like this!
I think put even more simply, this breakthrough is enticing because if you stack transistors, it's like taking an elevator to another floor instead of walking to a different office across the street (and since electricity is literally limited by the speed of light, then theoretically reducing the distance between transistors could increase the clock speed).
As you said, in practice the technology is going to need more time to mature, so I'm interested in reading more about this as more is developed.
Your elevator analogy is basically the whole pitch. Shorten the path a signal has to travel and you stop paying the speed-of-light tax on it, so the chip can run faster at the same power. That's the entire reason anyone's chasing this.
The piece you might be missing is smaller than it feels. Chips get built from the bottom up, more like a 3D printer, printing in reverse, rather than a sculptor; each ultra-thin layer is laid down on top of the last one. The light's only job is to pattern a stencil that decides where the next material goes, and the silicon itself stays untouched. The extra layers just come from stacking upward over and over, which the industry's quietly been doing for decades.
The catch, and why this might not pan out, is a thermal trap. The wiring already stacks 20-ish layers like this no problem. Stacking the actual transistors is the hard part, because making a good transistor means baking the silicon screaming hot, and baking a second layer that hot cooks the finished one sitting underneath it. Bake cooler to spare the bottom and the top layer comes out slow. Add the yield problem, where you bond two wafers and a single defect on either one ruins both, and you've got a real wall.
So I definitely agree it at least needs time. And that’s what the reference flow is for; plug in real public chip numbers and check whether the speed you'd actually gain beats the heat and yield penalties, instead of taking a lab-demo headline at face value. I'd love to see someone crack it, but so far the flat chip keeps winning that math.